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NB7L572 2.5V / 3.3V Differential 4:1 Mux Input to 1:2 LVPECL Clock/Data Fanout / Translator
Multi-Level Inputs w/ Internal Termination
The NB7L572 is a high performance differential 4:1 Clock/Data input multiplexer and a 1:2 LVPECL Clock/Data fanout buffer. The INx/INx inputs includes internal 50 W termination resistors and will accept differential LVPECL, CML, or LVDS logic levels. The NB7L572 incorporates a pair of Select pins that will choose one of four differential inputs and will produce two identical LVPECL output copies of Clock or Data operating up to 7 GHz or 10 Gb/s, respectively. As such, NB7L572 is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The NB7L572 INx/INx inputs, outputs and core logic are powered by a 2.5 V $5% V or 3.3 V $10% power supply. The two differential LVPECL outputs will swing 750 mV when externally terminated with a 50 W resistor to VCC - 2 V, and are optimized for low skew and minimal jitter. The NB7L572 is offered in a low profile 5x5 mm 32-pin QFN Pb-free package. Application notes, models, and support documentation are available at www.onsemi.com. The NB7L572 is a member of the GigaCommTM family of high performance clock products.
Features
http://onsemi.com MARKING DIAGRAM*
32 1 32 1 NB7L 572 AWLYYWWG
QFN32 MN SUFFIX CASE 488AM A WL YY WW G
= Assembly Site = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
IN0 50W VT0 50W IN0 VREFAC0 IN1 50W VT1 50W IN1 VREFAC1 IN2 50W VT2 50W IN2 VREFAC2 IN3 50W VT3 50W IN3 VREFAC3 SEL0 SEL1 0 Q0 Q0 Q1 Q1 3
* * * * * * * * * * * * * *
Input Data Rate > 10.7 Gb/s Typical Data Dependent Jitter < 15 ps Maximum Input Clock Frequency > 7 GHz Typical Random Clock Jitter < 0.8 ps RMS Low Skew 1:2 LVPECL Outputs, < 15 ps max 4:1 Multi-Level Mux Inputs, Accepts LVPECL, CML LVDS 150 ps Typical Propagation Delay 45 ps Typical Rise and Fall Times Differential LVPECL Outputs, 750 mV Peak-to-Peak, Typical Operating Range: VCC = 2.375 V to 3.6 V Internal 50 W Input Termination Resistors VREFAC Reference Output -40C to +85C Ambient Operating Temperature These are Pb-Free Devices
1 2
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2008
December, 2008 - Rev. 1
1
Publication Order Number: NB7L572/D
NB7L572
VREFAC3 VREFAC2
VT3
VT2
IN3
IN3
IN2
IN2
Exposed Pad (EP)
32
31
30
29
28
27
26
25
IN0 VT0 VREFAC0 IN0 IN1 VT1 VREFAC1 IN1
1 2 3 4 5 6 7 8
24 23 22 21 20 19 18 17
GND VCC Q1 Q1 VCC NC SEL1 VCC
NB7L572
10
12
13
14
15 SEL0
Q0
GND
Q0
VCC
VCC
NC
Figure 1. Pinout Configuration (Top View)
Table 1. INPUT SELECT FUNCTION TABLE
SEL1* 0 0 1 1 SEL0* 0 1 0 1 Clock / Data Input Selected IN0 Input Selected IN1 Input Selected IN2 Input Selected IN3 Input Selected
*Defaults HIGH when left open.
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VCC
16
11
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NB7L572
Table 2. PIN DESCRIPTION
Pin 1, 4 5, 8 25, 28 29, 32 2, 6 26, 30 15 18 14, 19 10, 13, 16 17, 20, 23 11, 12 21, 22 9, 24 3 7 27 31 - Name IN0, IN0 IN1, IN1 IN2, IN2 IN3, IN3 VT0, VT1 VT2, VT3 SEL0 SEL1 NC VCC Q0, Q0 Q1, Q1 GND VREFAC0 VREFAC1 VREFAC2 VREFAC3 EP - LVTTL/LVCMOS Input - - LVPECL Output I/O LVPECL, CML, LVDS Input Description Non-inverted, Inverted, Differential Clock or Data Inputs.
Internal 100 W Center-tapped Termination Pin for INx / INx Input Select pins, default HIGH when left open through a 28k-W pull-up resistor. Input logic threshold is VCC/2. See Select Function, Table 1. No Connect Positive Supply Voltage. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Inverted, Non-inverted Differential Outputs. Negative Supply Voltage, connected to Ground Output Voltage Reference for Capacitor-Coupled Inputs
-
The Exposed Pad (EP) on the QFN-32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is electrically connected to the die, and must be electrically connected to GND.
1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or left open, and if no signal is applied on INx / INx input, then the device will be susceptible to self-oscillation. 2. All VCC, and GND pins must be externally connected to a power supply for proper operation.
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NB7L572
Table 3. ATTRIBUTES
Characteristic ESD Protection Input Pullup Resistor (RPU) Moisture Sensitivity (Note 3) Flammability Rating Oxygen Index: 28 to 34 Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. QFN32 Human Body Model Machine Model Value > 4 kV > 150 V 28 kW Level 1 UL 94 V-0 @ 0.125 in 205
Table 4. MAXIMUM RATINGS
Symbol VCC VIN VINPP Iout IIN TA Tstg qJA qJC Tsol Positive Power Supply Positive Input Voltage Differential Input Voltage |IN - IN| LVPECL Output Current Input Current Through RT (50 W Resistor) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 4) Thermal Resistance (Junction-to-Case) (Note 4) Wave Solder v 20 sec 0 lfpm 500 lfpm QFN-32 QFN-32 QFN-32 Continuous Surge Parameter Condition 1 GND = 0 V GND = 0 V Condition 2 Rating -0.5 to +4.0 -0.5 to VCC +0.5 1.89 50 100 $40 -40 to +85 -65 to +150 31 27 12 265 Unit V V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7L572
Table 5. DC CHARACTERISTICS POSITIVE LVPECL OUTPUT VCC = 2.375 V to 3.6 V, GND = 0 V, TA = -40C to +85C
(Note 6) Symbol POWER SUPPLY VCC ICC VOH Power Supply Voltage VCC = 2.5V VCC = 3.3 V 2.375 3.0 2.5 3.3 90 2.625 3.6 110 V mA Characteristic Min Typ Max Unit
Power Supply Current for VCC (Inputs and Outputs Open) Output HIGH Voltage (Note 6) VCC - 1145 1355 2155 VCC - 2000 500 1300
LVPECL OUTPUTS VCC = 2.5 V VCC = 3.3 V VCC = 2.5 V VCC = 3.3 V VCC - 900 1600 2400 VCC - 1700 800 1600 VCC - 825 1675 2475 VCC - 1500 1000 1800 mV
VOL
Output LOW Voltage (Note 6)
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 4 & 6) (Note 7) VIH VIL Vth VISE VREFAC VREF-AC VIHD VILD VID VCMR IIH IIL VIH VIL IIH IIL RTIN Output Reference Voltage (100 mA Load) VCC - 1500 1200 0 100 1150 -150 -150 VCC - 1200 VCC - 1000 VCC VIHD - 100 1200 VCC - 50 150 150 mV Single-Ended Input HIGH Voltage Single-Ended Input LOW Voltage Input Threshold Reference Voltage Range (Note 8) Single-Ended Input Voltage (VIH - VIL) Vth + 100 GND 1100 200 VCC Vth - 100 VCC - 100 1200 mV mV mV mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 5 & 7) (Note 9) Differential Input HIGH Voltage (IN, IN) Differential Input LOW Voltage (IN, IN) Differential Input Voltage (IN, IN) (VIHD - VILD) Input Common Mode Range (Differential Configuration, Note 10) (Figure 8) Input HIGH Current IN/IN (VT IN/VT IN Open) Input LOW Current IN/IN (VT IN/VT IN Open) mV mV mV mV mA mA
CONTROL INPUT (SELx Pin) Input HIGH Voltage for Control Pin Input LOW Voltage for Control Pin Input HIGH Current Input LOW Current -215 2.0 GND VCC 0.8 40 0 V V mA mA
TERMINATION RESISTORS Internal Input Termination Resistor (Measured from INx to VTx) 45 50 55 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and Output parameters vary 1:1 with VCC. 6. LVPECL outputs loaded with 50 W to VCC - 2V for proper operation. 7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single-ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal.
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Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V, GND = 0 V, TA = -40C to +85C (Note 11)
Symbol fMAX fDATAMAX VOUTPP tPLH, tPHL tPD Tempco tskew tDC tJITTER VINPP tr,, tf Characteristic Maximum Input Clock Frequency VOUT w 400 mV Maximum Operating Data Rate NRZ, (PRBS23) Output Voltage Amplitude (@ VINPPmin) (Figure 2 & 9) (Note 12) Propagation Delay to Differential Outputs Measured at Differential Cross-Point fin 5 GHz fin 7 GHz Min 7 10 550 400 125 300 Typ 8 11 750 500 150 115 0 45 fin v 7.0 GHz fin v 10 Gbps 100 25 45 50 0.5 6 10 50 55 0.8 15 1200 65 175 1000 Max Unit GHz Gbps mV ps fs/C ps % ps rms ps pk-pk mV ps
@ 1 GHz INx/INx to Qx/Qx (Figure 9) @ 50 MHz SELx to Qx (Figure 10)
Differential Propagation Delay Temperature Coefficient Output - Output skew (within device) (Note 13) Device - Device skew (tpd max - tpd min) Output Clock Duty Cycle (Reference Duty Cycle = 50%) Additive Random Clock Jitter, RJ(RMS) (Note 14) Data Dependent Jitter, DDJ (Note 15) Input Voltage Swing (Differential Configuration) (Note 16) Output Rise/Fall Times @ 1 GHz; (20% - 80%), VIN = 800 mV Q, Q
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a 100 mVpk-pk source, 50% duty cycle clock source. All output loading with external 50 W to VCC - 2 V. Input edge rates 40 ps (20% - 80%). 12. Output voltage swing is a single-ended measurement operating in differential mode. 13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from cross-point of the inputs to the cross-point of the outputs. 14. Additive RMS jitter with 50% duty cycle clock signal. 15. Additive Peak-to-Peak data dependent jitter with input NRZ data at K28.5. 16. Input voltage swing is a single-ended measurement operating in differential mode. OUTPUT VOLTAGE AMPLITUDE (mV) 800 VCC 750
700
INx 50 W VTx 50 W INx
650
600 0 1 2 3 4 5 6 7 8 fin, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Input Structure
Figure 2. CLOCK Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (typical)
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NB7L572
VIH Vth VIL IN Vth IN IN IN
Figure 4. Differential Input Driven Single-Ended
Figure 5. Differential Inputs Driven Differentially
VCC Vthmax
VIHmax VILmax VIH Vth VIL VIHmin VILmin VID = |VIHD(IN) - VILD(IN)| VIHD VILD
Vth Vthmin GND
IN IN
IN
Figure 6. Vth Diagram
VCC VCMmax VIHDmax VILDmax IN IN VIHDtyp VID = VIHD - VILD VILDtyp VIHDmin VILDmin IN IN Q Q
Figure 7. Differential Inputs Driven Differentially
VINPP = VIH(IN) - VIL(IN)
VCMR
VOUTPP = VOH(Q) - VOL(Q) tPHL
VCMmin GND
tPLH
Figure 8. VCMR Diagram
Figure 9. AC Reference Measurement
SELx
VCC/2 tPHL
VCC/2 tPLH
Qx Qx
Figure 10. SELx to Qx Timing Diagram
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NB7L572
Q Driver Device Q Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device
VTT VTT = VCC - 2.0 V
Figure 11. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
VCC VCC VCC VCC
NB7L572 ZO = 50 W VT = VCC - 2 V ZO = 50 W D D 50 W 50 W LVDS Driver ZO = 50 W VT = Open ZO = 50 W D D
NB7L572
LVPECL Driver
50 W 50 W
VEE VCC
Figure 12. LVPECL Interface
VEE VCC
VEE VCC
Figure 13. LVDS Interface
VEE VCC
NB7L572 ZO = 50 W VT = VCC ZO = 50 W D D 50 W 50 W Differential Driver ZO = 50 W VT = VREFAC* ZO = 50 W D D
NB7L572
CML Driver
50 W 50 W
VEE
VEE
VEE
Figure 14. Standard 50 W Load CML Interface
*VREFAC bypassed to ground with a 0.01 mF capacitor
Figure 15. Capacitor-Coupled Differential Interface (VT Connected to VREFAC)
VEE
ORDERING INFORMATION
Device NB7L572MNG NB7L572MNR4G Package QFN32 (Pb-Free) QFN32 (Pb-Free) Shipping 79 Units / Rail 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB7L572
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P CASE 488AM-01 ISSUE O
A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
D
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X
8
32 X b 0.10 C A B
0.05 C BOTTOM VIEW
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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EE EE
TOP VIEW SIDE VIEW
9
PIN ONE LOCATION
E
(A3) A A1 C
EXPOSED PAD 16 SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
SOLDERING FOOTPRINT*
5.30 3.20 0.63
32 X
D2
K
17 32 X
E2
1 32 25 24
3.20
5.30
e 0.28
32 X
0.50 PITCH
28 X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB7L572/D

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